International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064

Downloads: 127 | Views: 257

Review Papers | Electronics & Communication Engineering | India | Volume 4 Issue 4, April 2015 | Rating: 6.4 / 10

A Comparative Study and Review of Different Clock Gating Techniques and their Application

Abhishek Sharma [11] | Ekta Jolly [2]

Abstract: With the increasing applications of electronics in day-2-day life and alteration in design techniques in the field of VLSI, we are required to design the ICs with maximum efficiency. By efficiency, here we mean the power consumption, the delays, operation at different frequencies and the stability of designed circuit. In this paper we have focused on the Clock Gating technique to decrease the dynamic power dissipation of CMOS based circuit, being an issue of great concern at higher clock rates. Further we analyzed a Clock Gating technique to observe difference in the power consumption in Johnson Counter. Doing some power analysis in SPICE, it is observed that proposed technique has lower power dissipation compared to the conventional design.

Keywords: Clock Gating CG, latch free clock gating, latch based clock gating, Flip-flop based gating, Clock gated Johnson Counter

Edition: Volume 4 Issue 4, April 2015,

Pages: 839 - 841

How to Download this Article?

Type Your Valid Email Address below to Receive the Article PDF Link

Verification Code will appear in 2 Seconds ... Wait