VLSI Chip Design for Abnormal Heartbeat Detection: Review

Nihalaparvin Abbas

Abstract: The detection of irregular heart rhythms from electrocardiogram (ECG) signals is essential for the diagnosis and continuous monitoring of cardiac disorders, where the early identification of arrhythmias, such as premature ventricular contractions, ventricular tachycardia, and ventricular fibrillation, is critical for preventing sudden cardiac events [7]?[9]. ECG analysis is challenged by noise, baseline drift, and nonstationary behavior, necessitating robust preprocessing and feature extraction techniques, such as wavelet-based denoising and moving average QRS detection methods [3], [10], [13]. Advanced heart rate variability (HRV) analysis using compressed sensing and integral pulse frequency modulation (IPFM) models has demonstrated improved spectral resolution and prognostic value, particularly for unevenly sampled RR intervals [4]?[6], [14]. Statistical, machine learning, and deep learning approaches, including Bayesian frameworks, complexity-measure-based hypothesis testing, and convolutional neural networks, have further enhanced arrhythmia detection and classification accuracy [7]?[9], [11], [15]. To support continuous real-time monitoring, recent research has emphasized hardware-efficient implementations, with VLSI, FPGA, and ASIC-based architectures enabling low-power abnormal heartbeat detection through optimized neural networks and edge artificial intelligence, which are suitable for wearable and implantable devices [1], [12], [16]?[18].

Keywords: Electrocardiogram (ECG), Abnormal Heartbeat Detection, Cardiac Arrhythmia, QRS Detection, Machine Learning, VLSI Design

How to Cite?: Nihalaparvin Abbas, "VLSI Chip Design for Abnormal Heartbeat Detection: Review", Volume 14 Issue 12, December 2025, International Journal of Science and Research (IJSR), Pages: 697-699, https://www.ijsr.net/getabstract.php?paperid=SR251208213556, DOI: https://dx.doi.org/10.21275/SR251208213556