International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 1 | Views: 147 | Monthly Hits: ⮙1

Research Paper | Electronics & Telecommunication Engineering | India | Volume 11 Issue 4, April 2022 | Rating: 4.2 / 10


Design of Low Power, Area Efficient and High Stability Multiple Frequency Output Phase Locked Loop for Multiphase Clocking Circuits

Pooja Thool | Dr. J. D. Dhande | Y. A. Sadawarte


Abstract: A phase locked loop (PLL) is a key element of many communication and instrumentation domain. It is a key element in clock generation. The proposed paper presents the design of low power, area efficient and high stability multiple frequency output of PLL using high performance and low power VCO for fast frequency locking. The PLL is designed in Microwind EDA in design environment using 32nm CMOS technology with operating frequency of 1 GHz and lock time of 100ns. We are using high performance VCO with wide frequency range of 1.59 GHz to 3.52 GHz. The PLL consumes total power of 0.118 mw with the technology supply voltage of 1 V. The PLL is designed with multiple output frequency locking as 3.67 GHz, 1.87 GHz, 0.86 GHz, and 0.42 GHz with an efficient area as 57.5?m2.


Keywords: Phase-locked loop, Phase frequency detector, low pass filter, voltage controlled oscillator, CMOS


Edition: Volume 11 Issue 4, April 2022,


Pages: 995 - 1000


How to Download this Article?

Type Your Valid Email Address below to Receive the Article PDF Link


Verification Code will appear in 2 Seconds ... Wait

Top