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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 5 Issue 5, May 2016

Realization of Programmable PRPG with Enhanced Fault Coverage Gradient

Lakshmi Asokan | Jeena Maria Cherian

Abstract: This paper describes a low power programmable pseudorandom pattern generator with desired toggling level and also enhanced fault coverage compared with other BIST based on PRPG. It comprised of finite state machine LFSR driving a phase shifter and it allows the device to produce binary sequence with preselected toggling activity. Generator is automatically controlled providing easy and precise tuning. Furthermore, this paper introduces a test compression method to avoid repeated pattern generation for testing the same device. The main highlight of this paper is to reduce the test data volume and test data memory.

Keywords: BIST, low power test, PRPG, test data volume compression

Edition: Volume 5 Issue 5, May 2016,

Pages: 2286 - 2288