Implementation of Space Time Block Codes for Wimax Applications
Abstract: This paper describes the concept, architecture, development and demonstration of a real time, maximum likelihood Alamouti decoder for a wireless 4-transmit 4-receiver multiple input and multiple output (MIMO) Smart Antenna Software Radio Test System (SASRATS) platform. It is implemented on a Xilinx Vertex 2 Pro Field Programmable Gate Array (FPGA). Hardware, firmware, use of the Xilinx Core Generator Intellectual Property modules and experimental verification of the decoder are discussed.
Keywords: real-time implementation, Alamouti, FPGA, maximum likelihood decoder, MIMO
How to Cite?: M Ravi, A Madhusudhan, "Implementation of Space Time Block Codes for Wimax Applications", Volume 2 Issue 3, March 2013, International Journal of Science and Research (IJSR), Pages: 52-56, https://www.ijsr.net/getabstract.php?paperid=IJSROFF2013077, DOI: https://dx.doi.org/10.21275/IJSROFF2013077