Design of Fixed One-Bit Latency Serdes Transceiver for High Speed Data Transmissions

Sangeetha N

Abstract: Today's communication world experiences a maximum amount of problems linked with serial interconnects since they occupy the entire communication field, therefore the serializer/deserializer (SerDes) devices make huge changes in the market with large differences in cost and performance. The serial interfaces are generally used for Transfer of information within chips and boards. The parallel interfaces were replaced by serial interconnects which were high speed as the bandwidth grew into multi-gigabit range. SerDes devices play an important role in exchanging information in this range. A SerDes device can compress the information, work in large bandwidth, and enables to exchange the information. It lowers the complexity associated with design, cost, and board space usage and signal strength compared with parallel connectors. The serial architecture in the present design depicts how the GTP transceiver which embeds the high speed SerDeses achieves a constant latency. Key words- Changeable Delay Tuning, Dynamic clock phase shifting, fixed onebit latency, FPGA, Serializer/deserializer.

Keywords: Changeable Delay Tuning, Dynamic clock phase shifting, fixed onebit latency, FPGA, Serializer/deserializer

How to Cite?: Sangeetha N, "Design of Fixed One-Bit Latency Serdes Transceiver for High Speed Data Transmissions", Volume 8 Issue 12, December 2019, International Journal of Science and Research (IJSR), Pages: 1192-1200, https://www.ijsr.net/getabstract.php?paperid=ART20203562, DOI: https://dx.doi.org/10.21275/ART20203562

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