Implementation of Low Power Adiabatic based Inverter for Dynamic Comparator

Heena Parveen, Vishal Moyal

Abstract: The requirement for portable battery operating devices is escalating nowadays, hence low power methodologies are being favoured for high speed applications. Symmetric circuits with regenerative feedback provide opportunity to spot new structures that may be mainly helpful. Regenerative feedback is generally used in Dynamic Comparators and hardly ever in non clocked comparators. In the process of designing high speed ADCs (Analog-to-Digital Converters), Dynamic Comparator is generally used and can be simply designed. Dynamic comparators have a wide use in high speed ADCs because of their fast speed, high input impedance, full-swing output and low power consumption. To further reduce the power consumption, a novel Dynamic Comparator has been proposed where the back-to-back inverter of a conventional dynamic comparator is being replaced by the DFAL (Diode Free Adiabatic Logic) inverter that utilizes the adiabatic logic principle. For the corroboration of performance, the design is simulated by the Cadence Virtuoso Spectre simulator in gdpk 90nm Technology.

Keywords: Conventional Dynamic Comparator, CMOS inverter, Adiabatic Logic, DFAL inverter