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M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 9, September 2015
296 - 300Reduction of Static Power Dissipation in CMOS Inverter using Extra Nodes and Substrate Current
Harigovind [3] | Sarath Mohan KP [2] | Mariya Stephen [3]
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M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015
1064 - 1068A Novel Architecture for High Quality Random Number Generation based on Enhanced WELL Method
Harigovind [3] | Vinoj P.G. [2]
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M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 8, August 2015
1627 - 1631Reduction of Static Power Dissipation in CMOS Inverter using Extra Nodes and Substrate Current
Harigovind [3] | Sarath Mohan KP [2] | Mariya Stephen [3]
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