Downloading: Design of IEEE - 754 Floating point Arithmetic Processor
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Design of IEEE - 754 Floating point Arithmetic Processor

J. Laxmi, R. Ramprakash

Abstract: In this paper, we deal with the designing of a 32-bit floating point arithmetic processor for RISC/DSP processor applications. It is capable of representing real and decimal numbers. The floating point operations are incorporated into the design as functions. The logic for these is different from the ordinary arithmetic functions. The numbers in contention have to be first converted into the standard IEEE floating point standard representation before any sorts of operations are conducted on them. The floating point representation for a standard single precision number is a 32-bit number that is segmented to represent the floating point number. The IEEE format consists of four fields, the sign of the exponent, the next seven bits are that of the exponent magnitude, and the remaining 24 bits represent the mantissa sign. The exponent in this IEEE standard is represented in excess-127 format all the arithmetic functions like addition, subtraction, multiplication and division will be design by the processor. The main functional blocks of floating point arithmetic processor design includes, Arithmetic logic unit(ALU), Register organization, control & decoding unit, memory block, 32-bit floating point addition, subtraction, multiplication and division blocks. This processor IP core can be embedded many places such as co-processor for embedded DSP and embedded RISC controller. The overall system architecture will be designed using HDL language and simulation, synthesis.

Keywords: single, dual precision, floating point, ALU, FPGA



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