Algorithm Feasibility on IoT Devices with Memory and Computational Power Constraints
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Research Paper | Computer Science & Engineering | India | Volume 8 Issue 5, May 2019

Algorithm Feasibility on IoT Devices with Memory and Computational Power Constraints

Anusha Medavaka

Internet of Things is a subject of much interest as well as, in last couple of years, safety of the IoT systems is a field of remarkable research activities. Shared verification between IoT devices as well as IoT web servers is a fundamental part of secure IoT systems. Solitary password-based verification mechanisms, which are commonly used, are vulnerable to side-channel and also dictionary attacks. In this paper, we present a multi-key (or multi-password) based shared verification device. In our strategy, the common key in between the IoT server as well as the IoT device is called protected vault, which is a collection of equal sized tricks. First components of the safe vault are shared in between the web server as well as the IoT device and components of the safe and secure vault modification after every successful communication session. We have implemented this device on an Arduino device to confirm our algorithm is practical on IoT devices with memory as well as computational power constraints.

Keywords: IoT Device Authentication, IoT Security, Secure Vault

Edition: Volume 8 Issue 5, May 2019

Pages: 1815 - 1820

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How to Cite this Article?

Anusha Medavaka, "Algorithm Feasibility on IoT Devices with Memory and Computational Power Constraints", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=ART20198261, Volume 8 Issue 5, May 2019, 1815 - 1820

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