Abstract: In Analog to digital convertor design converter, high speed comparator influences the overall performance of Analog to Digital Converter (ADC) directly. This paper presents the CMOS comparator for effective ADC at low power dissipation. A schematic design of this comparator is given with 1m Technology and simulated in HSPICE. Simulation results are presented and the design has DC Gain of 68dB, power dissipation of 1.25 mW at 5 V for 1um and the design has DC Gain of 18dB, power dissipation of 325 mW at 1.2V for 45 nm using HSPICE software.
Keywords: Comparator, ADC, Low Power, CMOS, Simulation, Design