International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 118

Review Papers | Electronics & Communication Engineering | India | Volume 4 Issue 1, January 2015


A Review on Implementation of Random Number Generation based on FPGA

Vishakha V. Bonde [2] | A. D. Kale [2]


Abstract: Random number generator is required extensively by many applications like cryptography, simulation, numerical analysis, text-to-speech etc. Most C libraries have a pair of library routines for initializing, and then generating random numbers. For parametric speech synthesis application, a random number generator is required to produce noise samples. Therefore, a need has been felt for the design of a dedicated hardware for random number generator that generates one random number per cycle so that text-to speech conversion is done in real time. A random number generator (RNG) is a device designed to generate a sequence of numbers or symbols that dont have any pattern. Hardware-based systems for random number generation are widely used, but often fall short of this goal, albeit may meet some of the statistical tests for randomness for ensuring that do not have any de-codable patterns.


Keywords: Random Number Generator, Cryptography, C, synthesis, text-to-speech, FPGA


Edition: Volume 4 Issue 1, January 2015,


Pages: 2749 - 2753


How to Download this Article?

You Need to Register Your Email Address Before You Can Download the Article PDF


How to Cite this Article?

Vishakha V. Bonde, A. D. Kale, "A Review on Implementation of Random Number Generation based on FPGA", International Journal of Science and Research (IJSR), Volume 4 Issue 1, January 2015, pp. 2749-2753, https://www.ijsr.net/get_abstract.php?paper_id=SUB15960

Similar Articles with Keyword 'Random Number Generator'

Downloads: 110

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 12, December 2015

Pages: 1804 - 1810

Optimization of FPGA Architecture for Uniform Random Number Generator Using LUT-SR Family

Rita Rawate | M. V. Vyawahare

Share this Article

Downloads: 113 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Survey Paper, Electronics & Communication Engineering, India, Volume 4 Issue 3, March 2015

Pages: 1590 - 1592

A Survey on Implementation of Random Number Generator in FPGA

Pallavi Bhaskar | Prof. P. D. Gawande

Share this Article
Top