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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 8, August 2015
8Kb Logic Compatible DRAM based Memory Design for Low Power Systems
Harshita Shrivastava | Rajesh Khatri
Abstract: 8Kb DRAM based memory is implemented for low power systems.3T DRAM gain cell utilizing preferential boosting is used to achieve large data retention time and low leakage current which contributes to low power consumption. Current mode sense amplifier is designed for read operation to achieve high speed which gives output in voltage mode. There are two 4Kb sections in memory architecture which are controlled by internal control circuitry. This architecture has simplest write back circuitry. This Design performs all specific memory functions. This test memory has 20 pins. This design is done in 180nm CMOS technology
Keywords: DRAM, Decoder, Sense amplifier, Control circuit, Logic gates
Edition: Volume 4 Issue 8, August 2015,
Pages: 1267 - 1271
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M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 5 Issue 1, January 2016
Pages: 1000 - 1002A New Technique of Auction Based Spectrum Allocation for CR Network
Jyoti Shivshankar Swami | Sangita Nikumbh [2]
Downloads: 115
Research Paper, Electronics & Communication Engineering, China, Volume 4 Issue 2, February 2015
Pages: 1743 - 1747Design and Implementation of an Accidental Fall Detection System for Elderly
Enku Yosef Kefyalew | Abubakr Rahmtalla Abdalla Mohamed [2]