8Kb Logic Compatible DRAM based Memory Design for Low Power Systems
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 8, August 2015

8Kb Logic Compatible DRAM based Memory Design for Low Power Systems

Harshita Shrivastava, Rajesh Khatri

8Kb DRAM based memory is implemented for low power systems.3T DRAM gain cell utilizing preferential boosting is used to achieve large data retention time and low leakage current which contributes to low power consumption. Current mode sense amplifier is designed for read operation to achieve high speed which gives output in voltage mode. There are two 4Kb sections in memory architecture which are controlled by internal control circuitry. This architecture has simplest write back circuitry. This Design performs all specific memory functions. This test memory has 20 pins. This design is done in 180nm CMOS technology

Keywords: DRAM, Decoder, Sense amplifier, Control circuit, Logic gates

Edition: Volume 4 Issue 8, August 2015

Pages: 1267 - 1271

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How to Cite this Article?

Harshita Shrivastava, Rajesh Khatri, "8Kb Logic Compatible DRAM based Memory Design for Low Power Systems", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB157372, Volume 4 Issue 8, August 2015, 1267 - 1271

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