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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 8, August 2015
Low Power 1 bit Adiabatic SRAM Cell Design
Shobha Goutam | D. K. Mishra [2]
Abstract: This paper presents the design of an Adiabatic static RAM with a bit line driver that reduces power dissipation by efficiently recovering energy from the bit capacitors in 180nm technology. Cadence simulations of a simple 1 bit Asymmetrical Adiabatic SRAM, that includes the energy recovering bit line drivers, and the sense amplifiers, show over 35 % of power savings at 1.8 V, in comparison with its conventional counterpart.
Keywords: SRAM Static Random Access Memory, Adiabatic circuitry, charge recovery low-energy design, low-power computing techniques
Edition: Volume 4 Issue 8, August 2015,
Pages: 329 - 332
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Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 8, August 2015
Pages: 1597 - 1602Design Of 7T SRAM Cell Using Self-Controllable Voltage Level Circuit to Achieve Low Power
Vema Vishnu Priya | G.Ramesh
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Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015
Pages: 1862 - 1867FPGA Based Architecture for High Performance SRAM Based TCAM for Search Operations
Lekshmipriya S. | Suby Varghese [2]