International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 124

Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 7, July 2015


Design of an FFT Processor using Mixed-Radix Algorithm for OFDM system

Jaishri Katekhaye | Amit Lamba


Abstract: A parallel Fast Fourier Transform (FFT) processor for the use in Orthogonal Frequency Division Multiplexing (OFDM) is proposed here. The proposed processor is 64-point which is based on mixed radix (4-2) algorithm and execute 16-bit fixed point data format. The clock cycles required for the FFT processor are 92 which are less in number due to the use of parallel processing. The delay required for simulation of 64-point FFT is 11.924ns. For simulation we used XILINX 14.2 ISE software and for coding we employed Very High Speed Integrated Circuit Hardware Description Language (VHDL).


Keywords: FFT, Mixed Radix, OFDM, VHDL


Edition: Volume 4 Issue 7, July 2015,


Pages: 415 - 419


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How to Cite this Article?

Jaishri Katekhaye, Amit Lamba, "Design of an FFT Processor using Mixed-Radix Algorithm for OFDM system", International Journal of Science and Research (IJSR), Volume 4 Issue 7, July 2015, pp. 415-419, https://www.ijsr.net/get_abstract.php?paper_id=SUB156318

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