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Case Studies | Electronics & Communication Engineering | India | Volume 4 Issue 2, February 2015

Re-Configurable Built In Self Repair scheme in Ram for Yield Improvement

Tessy M John | Dhanya Oommen

Abstract: The usage of embedded memories is more than half of the die area for a typical system on chip (SOC). Due to the complexity of memory architectures, the possibility of occuring manufacturing defects is more. Hence memory testing is at high risk. Built In Self Test (BIST) has been proven to be most costeffective and widely used solutions for memory testing. It is a mechanism that allows a machine or a circuit to test itself. BIST module consist of a test pattern generator, circuit under test and a response analyzer. The generated test patterns are applied to circuit under test and the test response is evaluated by an output response analyzer. From the output of output response analyzer, the faulty circuit can be detected. The faults detected during testing is repaired using a suitable repairing method. Built In Self Repair (BISR) techniques are widely used for repairing embedded memories. The earlier repairing methods have low repair rate and takes lot of time to repair. BISR technique is used to reduce repair time and to increase the repair rate. The design architecture is Simulated using ModelSim and Xilinx ISE 13.1 tools. Most of the repairing are based on allocating some redundancy to memory elements. For allocating redundancy, redundancy analysis is necessary. An efficient redundancy analysis method called Re-Configurable Built In Redundancy Analysis is used to improve repair rate and to reduce repair time.

Keywords: BIST, BISR, FPGA, BIRA

Edition: Volume 4 Issue 2, February 2015,

Pages: 1937 - 1941

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