International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 125

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 2, February 2015


Fault Tolerant Linear State Machine Design Approach for Safety Critical Systems Implemented on FPGA

Sunanda [27] | Fathima Rehana


Abstract: In this paper, a new method for the design of fault tolerant linear state machines with initial state 0 and one dimensional input and one-dimensional output is proposed. It is shown that the LFSR-implementation of the transfer function of a linear automaton can be utilized to correct transient errors in the memory elements. Since the state vector of a linear automaton is uniquely determined by the last n inputs and outputs, a transient error in a memory element can be corrected within n clock cycles by use of the corrected output symbols, where n is the number of components of the state vector


Keywords: TMR tripple modular redundancy, Voter logic


Edition: Volume 4 Issue 2, February 2015,


Pages: 1635 - 1636


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How to Cite this Article?

Sunanda, Fathima Rehana, "Fault Tolerant Linear State Machine Design Approach for Safety Critical Systems Implemented on FPGA", International Journal of Science and Research (IJSR), Volume 4 Issue 2, February 2015, pp. 1635-1636, https://www.ijsr.net/get_abstract.php?paper_id=SUB151574

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