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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 1, January 2015
An Efficient Design for Reduction of Power Dissipation in Johnson Counter using Clock Gating
Bhima Venkata Sujatha | V. T. Venkateswarlu
Abstract: In this paper, a new method for minimizing power dissipation in 4-bit Johnson up-down counter is proposed. In this design, we have used a dual dynamic pulsed flip-flop (DDFF) [1], which supports embedding a logic module (DDFF-ELM) and a power saving technique, namely, clock gating [2] is used. We have used DDFF because it is power efficient compared to other flip-flops in the literature. We have used digital schematic editor (DSCH) for designing, simulation and layout generation is done using Microwind. From the simulation results, it is observed that power dissipation is reduced by 33.9 %.
Keywords: Johnson counter, DDFF-ELM, DSCH, Microwind, clock gating
Edition: Volume 4 Issue 1, January 2015,
Pages: 2723 - 2728
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M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015
Pages: 2374 - 2378Circuit under Test Verification with MSIC Test Pattern Generator
Parvathy Chandra | Vishnu V. S. [2]
Downloads: 127
Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015
Pages: 839 - 841A Comparative Study and Review of Different Clock Gating Techniques and their Application
Abhishek Sharma [11] | Ekta Jolly [2]