Downloading: Efficient Hardware Utilization for Functional Broadside Test to Achieve High Fault Coverage
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Most Trusted Research Journal Since Year 2012

ISSN: 2319-7064



Your Article PDF will be Downloaded in Next Seconds

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 9, September 2014

Efficient Hardware Utilization for Functional Broadside Test to Achieve High Fault Coverage

P. Durga Venkata Prasad, K. Tirumala Rao

Functional broadside tests are two-pattern scan-based tests that avoid over testing by ensuring that a circuit traverses only reachable states during the functional clock cycles of a test. On-chip test generation has the added advantage that it reduces test data volume and facilitates at-speed test application. This paper shows that on-chip generation of functional broadside tests can be done using simple hardware, and can achieve high transition fault coverage forte stable circuits. With the proposed on-chip test generation method, the circuit is used for generating reachable states during test application. This alleviates the need to compute reachable states off-line

Keywords: Built-in test generation, functional broadside tests, reachable states, transition faults

Edition: Volume 3 Issue 9, September 2014

Pages: 1938 - 1943

Share this Article

How to Cite this Article?

P. Durga Venkata Prasad, K. Tirumala Rao, "Efficient Hardware Utilization for Functional Broadside Test to Achieve High Fault Coverage", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SEP14536, Volume 3 Issue 9, September 2014, 1938 - 1943



Top