International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 104

Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 10, October 2014


Implementation of Low Power Ternary Logic Gates using CMOS Technology

V. T. Gaikwad [3] | Dr. P. R. Deshmukh


Abstract: This paper describes the architecture, design & simulation of ternary logic gates. In a VLSI circuit, approximately 70 percent of the area is devoted to interconnection, 20 percent to insulation, and 10 percent to devices. The binary logic is limited due to interconnect which occupies large area on a VLSI chip. In this work, the designs of ternary-valued logic circuits have been explored over multi-valued logic. The proposed GATES are designed & simulated with the help of Microwind EDA tool. s. These Gates are implemented using C-MOS ternary logic (T-Gates) The new family is based on CMOS technology and is thus open to VLSI implementation. The proposed design is comprised of a set of inverters, NOR gates, and NAND gates. The designed technique used here requires the width and length calculations of the CMOS gates to improve thef the design. The proposed logic can be implemented at its layout side using 45 nm technologies.


Keywords: Ternary, Multi valued logic, CMOS, VLSI


Edition: Volume 3 Issue 10, October 2014,


Pages: 2221 - 2224


How to Download this Article?

You Need to Register Your Email Address Before You Can Download the Article PDF


How to Cite this Article?

V. T. Gaikwad, Dr. P. R. Deshmukh, "Implementation of Low Power Ternary Logic Gates using CMOS Technology", International Journal of Science and Research (IJSR), Volume 3 Issue 10, October 2014, pp. 2221-2224, https://www.ijsr.net/get_abstract.php?paper_id=OCT14633

Similar Articles with Keyword 'Ternary'

Downloads: 105 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1

Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 1862 - 1867

FPGA Based Architecture for High Performance SRAM Based TCAM for Search Operations

Lekshmipriya S. | Suby Varghese [2]

Share this Article

Downloads: 105

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 1843 - 1847

Design of 8 x 8 Vedic Multiplier using Quaternary-Logic & Pipelining Architecture

Vivek D. Wanjari | Prof. R. N. Mandavgane [2] | Prof. Shailesh Sakhare

Share this Article
Top