International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 104

Research Paper | Electronics & Communication Engineering | India | Volume 5 Issue 3, March 2016


Implementation of Data Encoding Techniques for Reducing Area, Power Consumption in Network-on-Chip for LDPC Applications

Vijaykumar Jadhav | K. Sujata


Abstract: As technology improves, the power dissipated by the links of a network-on-chip (NoC) starts to compete with the power dissipated by the other elements of the communicate ion subsystem, namely, the routers and the network interfaces (NIs). Here, we present a set of data encoding schemes to reduce the power dissipated by the links of a NoC. In this paper, the encoder in LDPC is replaced with our data encoding schemes in order to reduce the power consumption in Low Density Parity Check Techniques. Experiments carried out on both synthetic and real traffic scenarios show the effectiveness of the proposed schemes


Keywords: Encoding, Interconnection On Chip, Low Density Parity Check, Majority Logic Decoding, Power Analysis


Edition: Volume 5 Issue 3, March 2016,


Pages: 2240 - 2243


How to Download this Article?

You Need to Register Your Email Address Before You Can Download the Article PDF


How to Cite this Article?

Vijaykumar Jadhav, K. Sujata, "Implementation of Data Encoding Techniques for Reducing Area, Power Consumption in Network-on-Chip for LDPC Applications", International Journal of Science and Research (IJSR), Volume 5 Issue 3, March 2016, pp. 2240-2243, https://www.ijsr.net/get_abstract.php?paper_id=NOV162344

Similar Articles with Keyword 'Encoding'

Downloads: 29

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 10 Issue 3, March 2021

Pages: 1263 - 1265

Dense Fusion of Infrared and Visible Images

Gopika Ajay | H. Shihabudeen

Share this Article

Downloads: 99

Review Papers, Electronics & Communication Engineering, India, Volume 5 Issue 4, April 2016

Pages: 2313 - 2315

Review of Fully Reused VLSI Architecture of Channel Encoding Using SOLS Technique for DSRC Applications

Supriya S. Garade | P. R. Badadapure [2]

Share this Article
Top