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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 12, December 2015
Hardware Implementation of Min-Sum Decoder for Low Density Parity Check Codes
Mamta Prakash [2] | Girraj Prasad Rathore [2]
Abstract: Low Density Parity Check (LDPC) technique is highly used in the communication protocol to effectively transfer data from transceiver end to receiver end. In this paper a highly efficient decoding technique viz. min-sum has used to transfer data. The data from the communication channel is used for the decoding process. Min-Sum algorithm decoder is implemented and simulation is done using Model sim. The hardware synthesis results are shown using Xilinx ISE 14.1 and Spartan 6 FPGA board.
Keywords: LDPC, Decoder, Min-sum Algorithm, FPGA
Edition: Volume 4 Issue 12, December 2015,
Pages: 1451 - 1453
Similar Articles with Keyword 'LDPC'
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Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 3, March 2016
Pages: 2240 - 2243Implementation of Data Encoding Techniques for Reducing Area, Power Consumption in Network-on-Chip for LDPC Applications
Vijaykumar Jadhav | K. Sujata
Downloads: 107
M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 3 Issue 11, November 2014
Pages: 2745 - 2749An Efficient Low Latency Low Complexity Architecture for Matching of Information Coded with Error-Correcting Codes
Sankareswari.M | Udhayakumar.S