International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 116

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 11, November 2015


Area Optimized Double Precision IEEE Floating Point Adder

Elizabeth Joseph Mattam | Deepa Balakrishnan


Abstract: The fields of science, engineering and finance require manipulating real numbers efficiently. Since the first computers appeared, many different ways of approximation real numbers on it have been introduced. One of them, the floating point arithmetic, is the most efficient way of representing real numbers in computers. Representing an infinite, continuous set of (real numbers) with a finite set of (machine numbers) is not an easy task some compromises must be found between speed, accuracy and efficient use and also implementation and memory cost. Floating Point Arithmetic represent a very good compromise for numerical applications. Floating Point (FP) addition, subtraction and multiplication are widely used in large set of scientific and signal processing computation. Although the concept of Floating-Point addition is easy it imposes a immense challenge while implementation of complex algorithm in hard real-time due to the enormous computational burden with repeated calculations with high precision numbers. A novel technique to implement a double precision IEEE floating-point adder which can complete the operation within two clock cycles. The proposed technique has exhibited improvement the operational chip area management by modifying the carry select adder. Also a decrease in power is also expected since area and power are directly proportional.


Keywords: Area optimized carry select adder, Floating point adder, area and power reduction, CSLA, Clock cycles


Edition: Volume 4 Issue 11, November 2015,


Pages: 344 - 347


How to Download this Article?

You Need to Register Your Email Address Before You Can Download the Article PDF


How to Cite this Article?

Elizabeth Joseph Mattam, Deepa Balakrishnan, "Area Optimized Double Precision IEEE Floating Point Adder", International Journal of Science and Research (IJSR), Volume 4 Issue 11, November 2015, pp. 344-347, https://www.ijsr.net/get_abstract.php?paper_id=NOV151129

Similar Articles with Keyword 'CSLA'

Downloads: 106

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015

Pages: 2242 - 2245

Design and Implementation of 64-Bit Multiplier Using CLAA and CSLA

Shaik Meerabi | Krishna Prasad Satamraju

Share this Article

Downloads: 112

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 2997 - 3000

Area Efficient architecture for 64 bit CSLA using Sum and Carry Generation Unit

Mahadev Bobade | M. N. Kakatkar

Share this Article
Top