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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 8 Issue 5, May 2019

Development of QA Cell for PDK Validation and Automation using Cadence Skill

Payel Das | Santanu Nandy

Abstract: Process Design Kit is a unied foundry specic data used to design an integrated circuit. it can be logically thought similar to molecular DNA for the semiconductor industry. With the help of this PDK, an VLSI engineer can jump-start to design a chip and work seamlessly through the entire Design ow i. e Schematic Entry to Tapeout. This PDK is provided by the foundry which is technology specic, but can be tailored by the company according to their design style and markets. The Designer can use this PDK to design, simulate and verify the design before handling them to foundry for chip production. More accurate the PDK, More the chances of rst pass successful silicon which in turn decreases the loss for the company. Cells are made with respect to the Design rules for various possible cases that an Designer may come across and then the DRC is made to run on the cells which gives us a check whether the DRC rules are properly coded or not to cover all the possible scenarios. if any discrepancies are found then they are xed and same procedure is repeated. In the another section of the project an attempt is made to reduce the time required for drawing the QA cells with the help of automation using Cadence SKILL Language which in turn makes the process of validation faster.

Keywords: QA Cell, Skill Automation, PDK

Edition: Volume 8 Issue 5, May 2019,

Pages: 120 - 122

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