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Research Paper | Electronics & Communication Engineering | India | Volume 7 Issue 6, June 2018

A Low Power CMOS 8T SRAM Cell for High Speed VLSI Design Using Transmission Gate Mode

Urvashi Chaudhary | Rajendra Bahadur Singh

Abstract: In power consumption, reduction makes a device more reliable. In recent years, the demand of low power devices has been increased and due to scaling of CMOS technology. Due to the scaling, the important advantage is the size of the chip decreases and the no. of transistors increases in a system of chip (SOC). Power consumption is the most attentive parameter to design low power devices because it plays an important role in increasing the total power consumption of the devices. VLSI technology has created throughout the years thereby upgrading the performance of chips in terms of three fundamental constraints namely. Delay, area and power. A low power design has now become a most important issue in VLSI design, basically for high speed and high performance systems. At the technology level, technology optimization is the final tool that a designer can use to produce low power and a high-performance of SRAMs. In this paper, the 8T SRAM Cell has been design and implemented on 90nm and 45nm technology by using CADENCE VIRTUOSO. For simulation we are using 1V power supply and at different frequency (500MHz, 1GHz and 2GHz).

Keywords: conventional 6T SRAM Cell, Transmission Gate TG, Delay, Power, PDP, VLSI circuit, integrated circuit IC

Edition: Volume 7 Issue 6, June 2018,

Pages: 1156 - 1159

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