Downloads: 136
Research Paper | Electronics & Communication Engineering | India | Volume 6 Issue 6, June 2017
An Ultra-Low-Power Frequency Multiplier based on Mixed-Mode DLL with Output Frequency from 4 to 6 GHz
Priyadharshini M | Paul Richardson Gnanaraj J
Abstract: An Ultra-Low-Power frequency multiplier based on Mixed-Mode DLL is presented in this paper. The operating frequency range is between 100 and 150 MHz which enables to produce output signals in the frequency range from 4 to 6 GHz. NAND-based delay cells are used in the digital part of the delay line due to their wide operating frequency range and small intrinsic delay. The analogue part of the delay line is based on the inverter delay chain with biasing circuit. It was added into the system to overcome the resolution problem and improve jitter performance. The total locking time changes from 10 to 14 clock cycles based on the operating frequency. The simulated peak-to-peak jitter is 21 ps and 1.95 ps for the generated clock operating at 5 GHZ and output clock of DLL operating at 125 MHz respectively.
Keywords: mixed-mode DLL, frequency generation, phase selection, jitter
Edition: Volume 6 Issue 6, June 2017,
Pages: 860 - 864
Similar Articles with Keyword 'jitter'
Downloads: 101
M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015
Pages: 1180 - 1185A Fast-Locking All-Digital Deskew Buffer with DCC using Digital-Controlled Delay Line
A.Ashwini | H. Shravan Kumar
Downloads: 106
Research Paper, Electronics & Communication Engineering, Sudan, Volume 6 Issue 5, May 2017
Pages: 1973 - 1975MPLS as Backbone for Site to Site VPN Networks in VOIP Applications
Mohamed Taj Alssir A/Rahman | Dr. Hala Aldaw [4]