Downloads: 169
M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 5 Issue 7, July 2016
DMC Based Router Architecture for Dynamic Network on Chip
Geethu Jayan | Pavitha P. P.
Abstract: Network on Chip is the most viable solution for establishing communication among various modules in a System on Chip. A modified Error correction and detection mechanism is proposed in this paper which is applicable for the Dynamic Network on Chip. In DyNoC, the position and the number of components may vary during runtime The architecture of an such an NoC router is considered and significant modifications are made in the error detection and correction regime. The architecture is modelled using VHDL in Xilinx ISE Design Suite 13.2.
Keywords: Network on Chip NoC, DyNoC, Error Correction, Routing Algorithm
Edition: Volume 5 Issue 7, July 2016,
Pages: 90 - 92
Similar Articles with Keyword 'Error Correction'
Downloads: 102
M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 5 Issue 9, September 2016
Pages: 1074 - 1075Developing a Scheme that Reduces the Protection Liability
Bonala Srinath | G. Purna Chender Rao
Downloads: 107
Case Studies, Electronics & Communication Engineering, India, Volume 4 Issue 2, February 2015
Pages: 1933 - 1936A Method of Error Detection and Correction Using Euclidean Geometry Low Density Parity Check Codes
Vrinda S Anand | Sukanya Sundaresh [2]