Downloads: 130
Research Paper | Electronics & Communication Engineering | India | Volume 5 Issue 12, December 2016
Design and Implementation of 16 X 16 High speed Vedic multiplier using Brent Kung Adder
Nidhi Singh [7] | Mohit Singh [4]
Abstract: In VLSI design, the performance of any system is determined by the performance of the elements i. e. Multiplier. Multiplier is the slow element in the system. The speed of multiplier depends on multiplication technique and type of adder. This paper proposes the architecture of 16 x 16 high speed binary arithmetic multiplier using Urdhva Tiryagbhyam sutra of Vedic mathematics. Urdhva Tiryagbhyam sutra is used for generating the partial products. The partial product addition in Vedic multiplier is realized using Brent Kung adder. The HDL used for design is Verilog and code is implemented in Xilinx ISE 14.7 software. The combinational path delay of 16x16 bit Vedic multiplier obtained after synthesis is compared with Vedic multiplier using MUX based adder and found that the proposed Vedic multiplier circuit seems to have better performance in terms of speed.
Keywords: Vedic Multiplier, Delay, VLSI, Brent Kung adder, Urdhva Tiryagbhyam Sutra, Verilog HDL
Edition: Volume 5 Issue 12, December 2016,
Pages: 239 - 242
Similar Articles with Keyword 'Vedic Multiplier'
Downloads: 2 | Weekly Hits: ⮙1 | Monthly Hits: ⮙1
Student Project, Electronics & Communication Engineering, India, Volume 10 Issue 9, September 2021
Pages: 122 - 125Design of 256 x 256 bit Vedic Multiplier
Aishwarya K M | Dr. Kiran V [4]
Downloads: 61
Masters Thesis, Electronics & Communication Engineering, India, Volume 9 Issue 12, December 2020
Pages: 1042 - 1046Renovated 32 Bit ALU Using Hybrid Techniques
Manju Davis | Uma N [6]