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M.Tech / M.E / PhD Thesis | Electrical Engineering | India | Volume 5 Issue 9, September 2016

A Scheme for Flag Identification in a Restricted Set Expression

Janagam Raghu | B. Ashok ^[2]

Abstract: The sign recognition problem continues to be investigated by many people scientists. An over-all theorem comes by creating the required conditions for sign recognition. First, an indication recognition formula for that restricted moduli set is described. The sign recognition unit is concurrent and appropriate for VLSI implementation in line with the suggested sign recognition formula. This brief presents a quick sign recognition formula for that residue number system moduli set. The brand new formula enables for parallel implementation and consists solely of modulo 2n additions. Then, an indication recognition unit for that moduli set is suggested in line with the new sign recognition formula. A typical RNS is determined solely for positive integers within the range (, M). To support negative integers, an implicit signed number system might be regarded as split up into an optimistic 1 / 2 of the number along with a negative 1 / 2 of the number. The system could be implemented one carry save adder, one comparator and something prefix adder. The experimental results show the suggested circuit unit offers 63.8 %, 44.9 %, and 67.6 % savings typically in area, delay and power, correspondingly, in comparison having a unit according to among the best sign recognition calculations. For any more realistic comparison, the 3 sign recognition models for those moduli set were implemented using static CMOS VLSI technology.

Keywords: Computer arithmetic, residue number system RNS, restricted moduli set, sign detection

Edition: Volume 5 Issue 9, September 2016,

Pages: 378 - 380

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