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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 8, August 2014
Leakage Power Reduction in CMOS XOR Full Adder Using Power Gating With GDI Technique
Piyush Sharma [3] | Ghanshyam Jangid [6]
Abstract: As technology scales into the nanometre regime leakage current, active power, delay and area are becoming important metric for the analysis and design of complex arithmetic logic circuits. low leakage 1bit full adder cells are proposed for mobile application, gated-diffusion input (GDI) technique have been introduced for further reduction in power.
Keywords: Power gating, GDI, 1-bit full adder, Sequential circuit, sleep transistors
Edition: Volume 3 Issue 8, August 2014,
Pages: 1731 - 1733
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Nayini Bhavani | Rahul D [14] | Bhavani Kiranmai | J. Yeshwanth Reddy
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Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015
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