Design of 1.8V, 72MS/s 12 Bit Pipeline ADC in 0.18μm Technology
Ravi Kumar, Seema Kanathe
This paper presents 12 bit pipeline ADC designed for the implementation of pipeline analog to digital converter. Designing includes TIQ comparator that reduces area and power consumption on a single chip. The general guideline is to design high speed, low power pipeline ADC with wide input bandwidth. Each block is designed at transistor level and design is simulated and verified on LT SPICE SWITCHER CAD-III schematic editor simulation tool using 0.18m technology. The simulation result shows that Sampling Rate is 72MS/s with power dissipation of 25mW with power supply having 1.8V.
Keywords: Single stage pipeline ADC, TIQ comparator, Sample and hold, high speed, low power
Edition: Volume 3 Issue 8, August 2014
Pages: 1374 - 1379