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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 8, August 2014
Leakage Power Reduction in 5-Bit Full Adder using Keeper & Footer Transistor
Narendra Yadav | Vipin Kumar Gupta [4]
Abstract: In the present scenario Power consumption plays an imperative role specifically in the field of VLSI. Every designer, either an analog circuit or a digital circuit designer is concerned about the amount of the power a circuit is going to consume in the end. The main objective of this project is to design and implement of the leakage power reduction in 5-bit Full Adder (Domino Logic and Transmission Gate) technology using of footer and Keeper transistor. Keeper and Footer transistor using Transmission gate or Domino Logic are used to cooperate in reduction static power dissipation in 5-Bit Full Adder. There is reduction of 72.18 % in power consumption by 5-bit transmission gate full adder with footer transistor as compared to 5-bit full adder on Tanner Tools.
Keywords: Domino Logic Style, Keeper transistor, Footer transistor, Transmission Gate, Feedback
Edition: Volume 3 Issue 8, August 2014,
Pages: 1100 - 1104
Similar Articles with Keyword 'Transmission Gate'
Downloads: 107
Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015
Pages: 3321 - 3325Comparative Study on Logic Gates Using Bulk Transmission Gate and Double Gate Transmission Gate
Sima Baidya | Arindam Chakraborty
Downloads: 111
M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 11, November 2015
Pages: 1025 - 1029Design and Analysis of Dynamic Comparator with Reduced Power and Delay
Shashank Shekhar [4] | Dr. S. R. P. Sinha [5]