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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 8, August 2014
Inculcation of Simultaneous Clock Gating and Power Gating in Sequential Design
Vivek Dadheech | Ghanshyam Jangid [6]
Abstract: This paper presents simultaneous use of clock gating and power gating in a sequential circuit, we have taken True Single Phase Clock (TSPC) FF. Clock gating is use to reduce the dynamic power whereas power gating technique is the best way to minimize the leakage current. If both the technique use in single circuit then we can minimize the power consumption and increase the performance of the circuit which also reduce the cost of the circuit, as also cost depends on the power consumption
Keywords: Clock gating, Power gating, TSPC FF, Sequential circuit
Edition: Volume 3 Issue 8, August 2014,
Pages: 757 - 759
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Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 1, January 2015
Pages: 2723 - 2728An Efficient Design for Reduction of Power Dissipation in Johnson Counter using Clock Gating
Bhima Venkata Sujatha | V. T. Venkateswarlu
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Review Papers, Electronics & Communication Engineering, India, Volume 4 Issue 7, July 2015
Pages: 1525 - 1530A Clock Gating Technique Using Auto Gated Flip Flop for Look Ahead Clock Gating
Mayuri B. Junghare | Aparna S. Shinde