Inculcation of Simultaneous Clock Gating and Power Gating in Sequential Design
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 8, August 2014

Inculcation of Simultaneous Clock Gating and Power Gating in Sequential Design

Vivek Dadheech, Ghanshyam Jangid

This paper presents simultaneous use of clock gating and power gating in a sequential circuit, we have taken True Single Phase Clock (TSPC) FF. Clock gating is use to reduce the dynamic power whereas power gating technique is the best way to minimize the leakage current. If both the technique use in single circuit then we can minimize the power consumption and increase the performance of the circuit which also reduce the cost of the circuit, as also cost depends on the power consumption

Keywords: Clock gating, Power gating, TSPC FF, Sequential circuit

Edition: Volume 3 Issue 8, August 2014

Pages: 757 - 759

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How to Cite this Article?

Vivek Dadheech, Ghanshyam Jangid, "Inculcation of Simultaneous Clock Gating and Power Gating in Sequential Design", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=2015493, Volume 3 Issue 8, August 2014, 757 - 759

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