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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014

Analysis of Clock Gating for Dynamic Power Reduction in JK Flip Flop with Transmission Gate

Neha Kumari ^[2] | Rakesh Jain ^[6]

Abstract: In this paper clock gating technique along with a comparator circuit is presented for low power VLSI (very large scale integration) circuit design. The rapid increase in the number of transistors on chips enabled a dramatic increase in the performance of computing systems. However, the performance improvement has been accompanied by an increase in power dissipation; thus requiring more expensive packaging and cooling technology. Reducing power dissipation is one of the most principle subjects in VLSI design today. Clock gating is a technique to reduce clock power with the help of transmission gate. In this paper 3bit JK flip flop is designed using transmission gate.3 bit JK flip-flop is constructed by connecting three JK flip-flops in series i. e. output of first JK flip-flop is fed as input of second JK flip-flop and the output of second JK flip-flop is fed as input of third JK flip-flop. Transmission gate has three input, called source, n-gate, and p-gate; and it has one output called drain. The transmission gate is simply the combination of two complementary transistors. Also a comparator circuit is added between input and output of JK flip flop. Simulation is perform by the Tanner tool and the experimental result shows that the clock gating technique is along with comparator circuit is able to reduce average power consumption. Average power is calculated in both the cases i. e. conventional JK flip-flop circuit and proposed JK flip-flop circuit. It is observed that approximately 16 % of dynamic power is saved.

Keywords: Transmission gate, Static power, Dynamic Power, JK flip flop, Clock gating etc

Edition: Volume 3 Issue 7, July 2014,

Pages: 206 - 209

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