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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 6, June 2014

Design and Verification of Truncation-Error-Tolerant 8 Bit Signed-Multiplier

Shruti Verma | Rakesh Jain ^[6]

Abstract: Multiplier is one of the essential element for microprocessors; digital signal processors etc. In this project; we had proposed architecture for high speed Truncation Multiplier Algorithm. In modern VLSI technology; the occurrence of all kinds of errors has always to be expected. There are some applications which accept small errors such as multimedia processing. Designing accurate circuit for these applications is waste of area/power. The proposed multiplier outperforms and provides significant improvement in power; area; and delay at the cost of little degrade in accuracy. In this paper; we designed and implemented a new high speed signed booth multiplier. We implemented 8 bit multiplier using the Radix -4 Booth Algorithm. The proposed multiplier reduces the partial product array due to which the area is minimized. This reduction in partial product increases the speed of the multiplier. For addition of partial product we use Ripple Binary Adder. The proposed multiplier is designed and implemented using verilog HDL in XILINX 9.2 version. Experimental results demonstrate that the proposed 8 bit approximate multiplier is 49.74 % faster and 77.83 % area efficient than conventional 8 bit signed multiplier.

Keywords: error-tolerant multiplier, Radix-4 booth multiplier, Ripple binary adder, Verilog, FPGA

Edition: Volume 3 Issue 6, June 2014,

Pages: 2700 - 2704

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