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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 6, June 2014

Implementation of Core-Lock Mechanism as A Data Synchronization Method in Embedded Multi-Core Systems

Megha.S | Dr C R Byrareddy

Abstract: Multi-core processors have become prevalent in the embedded systems for High-performance computations especially in the high-end digital applications. One of the major challenges in multi-core system is Data synchronization which facilitates the simultaneous execution of multiple threads in the same processor environment. Traditional methods solved the Data Synchronization issues using Lock based methods like semaphores or mutual exclusion of critical data. More advanced methods use transactional memory to achieve the same purpose. But there are advantages and disadvantages in both methods. So we propose a mechanism which exploits advantages of Traditional Lock based methods and evolving transactional memory methods. This Hybrid method will be termed as Core Locking (C-Lock) which is performance and energy efficient. C-Lock allows parallelism by detecting true conflicts and disables the clocks of the idle cores thereby minimizing the dynamic power consumption. This paper aims to implement the C-Lock manager using Verilog HDL; simulated using Cadence ncsim and synthesized using Cadence RTL compiler.

Keywords: Multi-core, Data Synchronization, embedded systems, energy, performance, Transaction memory TM

Edition: Volume 3 Issue 6, June 2014,

Pages: 2425 - 2430

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