International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed

ISSN: 2319-7064


Downloads: 107

Review Papers | Electronics & Communication Engineering | India | Volume 3 Issue 7, July 2014


Performance Analysis of Voltage Scaled Low Power Clock Distribution Network with Different Frequencies

Deepak P. Jose | C. P Sureshkumar


Abstract: Clock distribution networks forms an inherent part of any digital circuit. It use a large part of the total circuit power, which is not worthy. Different techniques are employed up till now to reduce the clock power. In this paper we have to demonstrate how clock power can be reduced significantly by distributing it at reduced supply voltage and analyse the power consumption of clock distribution network with different frequencies like 100 MHz, 200 MHz, 250 MHz, 400 MHz, and 1 GHz etc. The clock distribution network is designed and simulated in 180 nm technology. Achieving power reduction of about 52 %, 48 %, 44 %, 38 %, 27 %and26 %respectively


Keywords: Low-power design, voltage scaling, clock networks, VLSI Very Large Scale Integration


Edition: Volume 3 Issue 7, July 2014,


Pages: 1386 - 1390


How to Download this Article?

You Need to Register Your Email Address Before You Can Download the Article PDF


How to Cite this Article?

Deepak P. Jose, C. P Sureshkumar, "Performance Analysis of Voltage Scaled Low Power Clock Distribution Network with Different Frequencies", International Journal of Science and Research (IJSR), Volume 3 Issue 7, July 2014, pp. 1386-1390, https://www.ijsr.net/get_abstract.php?paper_id=20141239

Similar Articles with Keyword 'voltage scaling'

Downloads: 111

Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 6, June 2015

Pages: 987 - 991

Wide Range Enable Level Shifter for Multi-Supply Voltage Designs

Puneet Patil | D Sheshachalam

Share this Article

Downloads: 116

M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 10, October 2015

Pages: 1118 - 1124

Improved Power Reduction and Aging Mitigation Using Gate Replacement and Voltage Scaling Techniques

Jibi K Kurian | Praveena S Kammath

Share this Article
Top