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Research Paper | Electronics & Communication Engineering | India | Volume 3 Issue 6, June 2014
Low Power Circuit Design Using Positive Feedback Adiabatic Logic
Arjun Mishra | Neha Singh [11]
Abstract: This paper presents an adiabatic logic family called positive feedback adiabatic logic circuits (PFAL). There is power reduction due to energy recovery in the recovery phase of the clock supply. The power dissipation comparison with the static CMOS logic is performed. The simulation is performed on cadence virtusuo using 180nm CMOS technology. The result shows that power reduction of 50 % to 70 % can be achieved over static CMOS within a practical operating frequency range.
Keywords: Adiabatic, CMOS, PFAL, ECRL, N-MOS, P-MOS
Edition: Volume 3 Issue 6, June 2014,
Pages: 43 - 45
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Research Paper, Electronics & Communication Engineering, India, Volume 5 Issue 4, April 2016
Pages: 2433 - 2438A Novel Design of Low Power 4:2 Compressor using Adiabatic Logic
Shaswat Singh Bhardwaj | Vishal Moyal [2]
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M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 4 Issue 5, May 2015
Pages: 1409 - 1413Design and Analysis of Asynchronous 16*16 Adiabatic Vedic Multiplier Using ECRL and EEAL Logic
C. S. Harmya Sreeja | N. Sri Krishna Yadav