Survey Paper | Electronics & Communication Engineering | India | Volume 3 Issue 5, May 2014
A Survey on Low Power TSPC and E-TSPC CMOS 2/3 Prescaler
Nemitha B, Pradeep Kumar B. P
This survey paper describes dynamic circuit techniques; raising only a single-phase clock which is never inverted. The implementation of a dual-modulus prescaler using an extension of the true-single-phase-clock (TSPC) technique; the extended TSPC (E-TSPC) ; is discussed. The E-TSPC consists of a set of composition rules for single-phase-clock circuits employing static; dynamic; latch; data precharged; and NMOS-like CMOS blocks. The power consumption and operating frequency of the extended true single-phase clock (E-TSPC) -based frequency divider is also discussed. The short-circuit power and the switching power in the E-TSPC-based divider are discussed. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology.
Keywords: TSPC, E-TSPC, Prescaler
Edition: Volume 3 Issue 5, May 2014
Pages: 665 - 670
How to Cite this Article?
Nemitha B, Pradeep Kumar B. P, "A Survey on Low Power TSPC and E-TSPC CMOS 2/3 Prescaler ", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=20131858, Volume 3 Issue 5, May 2014, 665 - 670