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International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 3 Issue 5, May 2014

Area and Delay Minimization of Radix-2k Feedforward FFT Architecture

A. Salai Kishwar Jahan, A. Indhumathi

The radix-2 was a milestone in the design of pipelined FFT hardware architectures. Later; radix-2 extended to radix-216.However; radix-216 was only proposed for single path delay feedback (SFD) architectures; but not for feedforward; also it called multi path delay commutator (MDC).The radix-216 feedforward Fast Fourier Transform architecture (FFT).In feedforward architectures radix-216 can be used for any number of parallel samples which is a power of two. Furthermore; both decimation in frequency (DIF) and decimation in time (DIT) decompositions can be used. In addition to this; the designs can achieve very high throughputs and reduce the spare complexity; which make them suitable for the most demanding applications. Indeed; the proposed radix-2k feedforward architectures require fewer hardware resources than parallel feedback ones; also called multi path delay feedback (MDF) ; when several samples in parallel must be processed. As result; the proposed radix-216 feedforward architectures not only offer an attractive solution for current applications; but also open up a new research line on feedforward structures.

Keywords: Fast Fourier Transform, Multi path delay feedback MDF, Pipelined Architecture

Edition: Volume 3 Issue 5, May 2014

Pages: 562 - 566

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How to Cite this Article?

A. Salai Kishwar Jahan, A. Indhumathi, "Area and Delay Minimization of Radix-2k Feedforward FFT Architecture", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=20131854, Volume 3 Issue 5, May 2014, 562 - 566



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