Ranjith Ram. A, Pramod. P
Abstract: Two innovative high-speed low power parallel 8-bit counter architectures are proposed. Then, High speed 8-bit frequency divider circuits using the proposed architectures are realized. The proposed parallel counter architectures consist of two sections The Counting Path and the State Excitation Module. The counting path consists of three counting modules in which the first module (basic module) generates future states for the two remaining counting modules. The State Excitation Module decodes the count states of the basic module and carries this decoding over clock cycles through pipelined DFF to trigger the subsequent counting modules. The existing 8-bit parallel counter architecture  consumed a total transistor count of 442 whereas the proposed parallel counters consumed only 274 transistors. The power dissipation of the existing parallel counter architecture and the proposed parallel counter architecture were 4.21mW (PINT) and 3.60mW (PINT) respectively at 250MHz. The worst case delay observed for the 8-bit counter using existing parallel counter architecture  and the proposed parallel counter architectures were 7.481ns, 6.737ns and 6.677ns respectively using Altera Quartus II. A reduction in area (transistor count) by 27.45 % and a reduction in power dissipation by 16.28 % are achieved for the frequency dividers using proposed counter architectures. Also a reduction in delay by 10.75 % and 7.62 % is achieved for the 8-bit frequency divider circuits using proposed counter methods I & II respectively.
Keywords: Counter, divide-by-m, frequency divider, high speed, low-power, modules, modulus