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Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 10, October 2013

Performance Evaluation of 1-Bit Full Adder using Hybridizing PTL and GDI Techniques

K. Mallikarjuna ^[2] | V. LakshmiVasudha

Abstract: Most of the VLSI applications, such as DSP, image & video processing, and microprocessors, extensively use logic gates and arithmetic circuits.1-bit full adder cell is the extensively use in arithmetic circuits. Gate diffusion input (GDI) a new technique of low-power digital combinational circuit designis described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. In this paper an area and power efficient 9T adder design has been presented by hybridizing PTL and GDI techniques. The proposed adder design consist of 5 NMOS and 4 PMOS. A PTL based 5T XOR-XNOR module has been proposed to improve area at 65nm technology and compared with the previous XOR-XNOR design. The proposed Hybrid full adder design is based on this area efficient 5T XOR-XNOR module design. To improve area and power efficiency a cascade implementation of XOR module has been avoided in the proposed full adder. Also the simulation of layout and parametric analysis has been done for the proposed full adder design. The performance of the proposed technique is evaluated and compared by implementing it in 8-bit CLA adder, 4-bit RCA adder, 4-bit CSkA adder, 4-bit CSelA adder, 4-bit CSaA adder, ,. Several logic circuits have been implemented in various design styles. Their properties are discussed; simulation results are reported, and presented.

Keywords: Gate Diffusion Input, Pass transistor logic, CMOS, VLSI

Edition: Volume 2 Issue 10, October 2013,

Pages: 210 - 216

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