Low Power 8 bit Analog to Digital Converter (ADC) in 180 nm CMOS Technology
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Research Paper | Electronics & Communication Engineering | India | Volume 2 Issue 7, July 2013

Low Power 8 bit Analog to Digital Converter (ADC) in 180 nm CMOS Technology

Harshit Dosi, Rekha Agrawal

Analog to Digital Converter (ADC) is developed for operating at ultra low supply votages. Circuit is realized in 180 nm CMOS technology. The pre-simulation of ADC has been achieved on Caadence Virtuoso. The purpose of this work to develope a biomedical application. The research is focused on the design of ADC with sampling rate 100KS/s. It has very low cost and high speed technology with relative medium resolution and accuracy. This implies it posseses a good trade off between speed and cost. R2R DAC is used with a different approch in which matching of resistors is more easier than a conventional ADC.

Keywords: Cadence, CMOS, DAC, Sampling rate, VLSI

Edition: Volume 2 Issue 7, July 2013

Pages: 417 - 418

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How to Cite this Article?

Harshit Dosi, Rekha Agrawal, "Low Power 8 bit Analog to Digital Converter (ADC) in 180 nm CMOS Technology", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=02013184, Volume 2 Issue 7, July 2013, 417 - 418

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