International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Double Blind Reviewed

ISSN: 2319-7064




Downloads: 121

M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 10, October 2015


An Efficient Design of Advanced Encryption Algorithm with FPGA

Soraisham Tarunjit Meitei | M. Rajmohan [2]


Abstract: A FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is performed using a reconfigurable 32-bit MicroBlaze processor embedded in the FPGA chip using RS232 to interface with PC to obtain a prototyped data encryption/decryption system. The iterative looping approach with block and key size of 128 bits, lookup table implementation of S-box will performed. Simulation results, data summary results are carried out with previous reported designs.


Keywords: AES, FPGA, encryption, decryption, Rijndael, block cipher


Edition: Volume 4 Issue 10, October 2015,


Pages: 771 - 776


How to Cite this Article?

Soraisham Tarunjit Meitei, M. Rajmohan, "An Efficient Design of Advanced Encryption Algorithm with FPGA", International Journal of Science and Research (IJSR), Volume 4 Issue 10, October 2015, pp. 771-776, https://www.ijsr.net/get_abstract.php?paper_id=SUB158727

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