M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 9, September 2015
A Low Power Highly Applicable Approach for Caches Based on STT-RAM Technology
Neethu Anna Sabu | Sreeja K. A.
Abstract: The static power dissipation of the peripheral circuits of STT-RAM instruction caches is reduced in this paper. The main goal is to detect the idle time of caches in advance and thereby reduce power consumption. The architecture was further modified to reduce power consumption and to avoid data loss. PEG is introduced along with the architecture. It was applied in ATM and compared with that of conventional RAM. It was implemented and evaluated by XILINX ISE 8.1i and achieved a greater reduction in power.
Keywords: STT-RAM technology, caches, PEG-cache
Edition: Volume 4 Issue 9, September 2015,
Pages: 1325 - 1327
How to Cite this Article?
Neethu Anna Sabu, Sreeja K. A., "A Low Power Highly Applicable Approach for Caches Based on STT-RAM Technology", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=SUB158308, Volume 4 Issue 9, September 2015, 1325 - 1327, #ijsrnet
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