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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 8, August 2015
Design and Implementation of Adiabatic Logic for Low Power Application
Vijendra Pratap Singh, Dr. S. R. P. Sinha
This paper shows a new Adiabatic approach known as Complementary Pass Transistor Adiabatic Logic. Power minimization is the first priority of VLSI designers. The dynamic power requirement of CMOS circuits is a major concern in the design of personal information systems and large computers. The clocking mechanism used in Adiabatic logic is different from those of standard CMOS circuits. The Recovery phase of the power clock is used to recover charge from the load capacitor. Adiabatic logic provides a way to reuse the energy stored in load capacitors rather than the conventional way of discharging the load capacitors to the ground and wasting this energy. This paper shows the low power dissipation of Adiabatic logic by presenting the results of various designs (an inverter, two input AND gate, two input NAND gate, two input XOR gate). All simulations are carried out by TSPICE 14.1 and technology used is 90nm.
Keywords: Adiabatic logic, CPAL, Energy Recovery, Static CMOS, Low Power, Energy dissipation, Power clock
Edition: Volume 4 Issue 8, August 2015
Pages: 930 - 934
How to Cite this Article?
Vijendra Pratap Singh, Dr. S. R. P. Sinha, "Design and Implementation of Adiabatic Logic for Low Power Application", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB157441, Volume 4 Issue 8, August 2015, 930 - 934
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