Designing Successive Approximation Register ADC by Using Double Tail Comparator
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064



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Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 7, July 2015

Designing Successive Approximation Register ADC by Using Double Tail Comparator

Neha Sharma, Rachna Manchanda

In high speed communication systems, data converters are most important for a transmission. Successive Approximation Register ADC is used as a sub-ADC of time interleaved ADC because its simplicity, linearity, low power consumption, and low latency. In this paper the double tail comparator is designed using Tanner 13.0 software and the power consumed is 1.467 Watt. Then it is implemented in the slowest Successive Approximation register and the power consumption is analyzed. It is noted that the power and speed is increased due to implementation of double tail comparator. Power consumption is reduced to great extent. In this paper, SAR ADC is designed in 0.65um CMOS technology with power supply of 0.705v for vinn and supply voltage for vinp is 0.710v. This design is working on 500MHz frequency. Delay, average power, maximum peak power is analyzed.

Keywords: SAR ADC, Double Tail Comparator

Edition: Volume 4 Issue 7, July 2015

Pages: 1648 - 1650

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How to Cite this Article?

Neha Sharma, Rachna Manchanda, "Designing Successive Approximation Register ADC by Using Double Tail Comparator", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB156715, Volume 4 Issue 7, July 2015, 1648 - 1650

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