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M.Tech / M.E / PhD Thesis | Electronics & Communication Engineering | India | Volume 4 Issue 7, July 2015

A Memory Efficient -Fully Parallel QC-LDPC Encoder

Vishnu Nampoothiri V | Sajith Sethu P

Abstract: Low-Density Parity Check codes are a special class of linear block codes widely used in communication and disk storage systems, due to their Shannon limit approaching performance and their favourable structure. A special class of LDPC codes, called QC-LDPC codes, allows for efficient hardware implementations of encoding and decoding algorithms by exploiting the structure of the Parity Check Matrix (PCM), which is composed of circulant permutation matrices. These codes have encoding advantage over other types of LDPC codes. In this paper an efficient QC-LDPC encoder and decoder are developed. Belief propagation algorithm is used for decoding. Overall system is developed in Matlab and performances are compared for different rates. This work also introduces a memory efficient high throughput VHDL implementation for the encoder. Due to their error correction strength, QC-LDPC codes have been recently adopted in several industrial standards such as wireless local area networks (Wi-Fi, IEEE802.11 n, ac, and ad) and Digital Video Broadcasting- Satellite- Second Generation (DVB-S2).

Keywords: QC-LDPC codes, Encoding algorithm, Multilevel Expansion, LU decomposition, Parallel LDPC encoder, Throughput

Edition: Volume 4 Issue 7, July 2015,

Pages: 323 - 327

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