International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
Since Year 2012 | Open Access | Double Blind Reviewed

ISSN: 2319-7064




Downloads: 121

Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 1, January 2015


Design of I2C Single Master Using Verilog

Shivani Mehrotra | Nisha Charaya


Abstract: This paper focuses on the design of I2C single master which consists of a bidirectional data line i. e. serial data line (sda) and serial clock line (scl). This protocol can support multiple masters. I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices and is used for faster devices to communicate with slower devices and each other without data loss. It requires only two lines for communication with two or more chips and can control a network of device chips with just two general purpose I/O pins whereas, other bus protocols require more pins and signals to connect devices. The complete module is designed in Verilog and simulated in ModelSIM.


Keywords: Verilog, ModelSIM, I2C bus, Master, Slave, SDA, SCL


Edition: Volume 4 Issue 1, January 2015,


Pages: 1897 - 1900


How to Cite this Article?

Shivani Mehrotra, Nisha Charaya, "Design of I2C Single Master Using Verilog", International Journal of Science and Research (IJSR), Volume 4 Issue 1, January 2015, pp. 1897-1900, https://www.ijsr.net/get_abstract.php?paper_id=SUB15631

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