Downloads: 111
Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 7, July 2015
Low Power PLL with Time Shift Circuit Using Parallel PFD Configuration
Dr. Manish Sharma, Asma Chishti
Abstract: In this work a low noise power efficient parallel-PFD PLL is proposed. Parallel circuit configuration improves the SNR of the circuit. The proposed circuit includes delay circuit with 8/9 frequency divider and a 3 stage VCO. For reducing more noise time shifted circuit by using VCO is proposed. The proposed design is simulated using Tanner EDA in 180nm technology. In terms of power consumption, band phase noise the new current comparison domino offers significant improvement compared to existing system
Keywords: PLL, PFD, DMP
Edition: Volume 4 Issue 7, July 2015,
Pages: 1144 - 1146
How to Cite this Article?
Dr. Manish Sharma, Asma Chishti, "Low Power PLL with Time Shift Circuit Using Parallel PFD Configuration", International Journal of Science and Research (IJSR), https://www.ijsr.net/get_abstract.php?paper_id=SUB156205, Volume 4 Issue 7, July 2015, 1144 - 1146
How to Share this Article?
Similar Articles with Keyword 'PLL'
Downloads: 107
Research Paper, Electronics & Communication Engineering, India, Volume 3 Issue 6, June 2014
Pages: 847 - 850Speed Analysis of Body Biased TSPC and ETSCPC Flip Flops
Nemitha B, Pradeep Kumar B. P
Downloads: 113
Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 9, September 2015
Pages: 1799 - 1802Single Phase Clock Distribution using Low Power VLSI Technology
Krishna Naik Dungavath, Dr V. Vijayalakshmi
Similar Articles with Keyword 'PFD'
Downloads: 115
Research Paper, Electronics & Communication Engineering, India, Volume 4 Issue 4, April 2015
Pages: 1441 - 1445Design of Low Power Phase Frequency Detectors and VCO using 45nm CMOS Technology
Rajani Kanta Sutar, M.Jasmin, S. Beulah Hemalatha
Downloads: 132
M.Tech / M.E / PhD Thesis, Electronics & Communication Engineering, India, Volume 7 Issue 5, May 2018
Pages: 727 - 732Design and Implementation of a PLL using a Single-Event-Transient Hardened-by-Design (SETHBD) Charge Pump
Pallavi. K. R, Dr. K. N. Muralidhara