Low Power PLL with Time Shift Circuit Using Parallel PFD Configuration
International Journal of Science and Research (IJSR)

International Journal of Science and Research (IJSR)
www.ijsr.net | Open Access | Fully Refereed | Peer Reviewed International Journal

ISSN: 2319-7064

Research Paper | Electronics & Communication Engineering | India | Volume 4 Issue 7, July 2015

Low Power PLL with Time Shift Circuit Using Parallel PFD Configuration

Dr. Manish Sharma, Asma Chishti

In this work a low noise power efficient parallel-PFD PLL is proposed. Parallel circuit configuration improves the SNR of the circuit. The proposed circuit includes delay circuit with 8/9 frequency divider and a 3 stage VCO. For reducing more noise time shifted circuit by using VCO is proposed. The proposed design is simulated using Tanner EDA in 180nm technology. In terms of power consumption, band phase noise the new current comparison domino offers significant improvement compared to existing system

Keywords: PLL, PFD, DMP

Edition: Volume 4 Issue 7, July 2015

Pages: 1144 - 1146

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How to Cite this Article?

Dr. Manish Sharma, Asma Chishti, "Low Power PLL with Time Shift Circuit Using Parallel PFD Configuration", International Journal of Science and Research (IJSR), https://www.ijsr.net/search_index_results_paperid.php?id=SUB156205, Volume 4 Issue 7, July 2015, 1144 - 1146

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